(a) Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the same. More particularly, the present invention relates to a wire, contact or contact hole of a semiconductor device and a method for manufacturing the same.
(b) Description of the Related Art
Typically, a semiconductor device is insulated from another semiconductor device or an exterior circuit. For an electrical connection thereof, a contact hole is formed in an insulating layer, and a conductive material such as a metal fills the contact hole.
However, integrated circuit design rules decrease as integration of semiconductor devices increases, and thus, gaps between semiconductor device (or integrated circuit) patterns are reduced. Accordingly, a gap filling characteristic of an interlayer insulating layer that insulates one pattern from another becomes more important. Accordingly, a flowable insulating layer such as a borophosphosillcate glass (BPSG) layer or a phosphosilicate glass (PSG) layer is typically used as the interlayer insulating layer.
Hereinafter, a conventional method for forming a wire or contact hole using such an interlayer insulating layer will be described in detail with reference to FIG. 1, FIG. 2A, and FIG. 2B.
Firstly, as shown in FIG. 2A (and in part in FIG. 1), a gate insulating layer 11, a gate 12, and an insulating spacer 13 are formed above a semiconductor substrate 10, and a source/drain junction region 14 is formed in the substrate 10. Then, a flowable interlayer insulating layer 15 such as a BPSG layer or a PSG layer is formed over the substrate so as to fill the gap between the gate 12 and the adjacent gate 17.
Subsequently, as shown in FIG. 2B (and in part in FIG. 1), the interlayer insulating layer 15 is etched to form a contact hole 16 partially exposing the junction region 14. In this case, the etching of the interlayer insulating layer 15 is performed such that contact hole 16 has an overcut etch profile and becomes fully open.
Subsequently, although not shown, a conductive material such as a metal is deposited on the interlayer insulating layer 15 so as to fill the contact hole 16, and the conductive material is patterned such that a wire contacting the junction region 14 may be formed.
However, as the integration of semiconductor devices becomes higher, the gap between the gates 12 and 17 becomes narrower. Therefore, an aspect ratio of the gap becomes bigger, that is, a height D1 of the gap becomes relatively larger than a width thereof. Consequently, even if a flowable insulating layer such as a BPSG layer or a PSG layer is used to form the interlayer insulating layer 15, the gap between the gates 12 may not be fully filled with the interlayer insulating layer 15, and a void 100 may occur in the interlayer insulating layer 15, as shown in FIG. 2A
In addition, since the contact hole has an overcut profile, the thickness D2 from the contact surface at the bottom of the contact hole 16 to a bottom of the junction region 14 is decreased as shown in FIG. 2B. In this case, a contact resistance characteristic of a wire may become problematic,
The above information disclosed in this background section is only for enhancement of understanding of the background of the invention and therefore, it may contain information that does not form information (e.g., prior art) that may be already known in this or any other country to a person or ordinary skill in the art